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MEMOCODE
2005
IEEE
16 years 12 days ago
Automatic synthesis of cache-coherence protocol processors using Bluespec
There are few published examples of the proof of correctness of a cache-coherence protocol expressed in an HDL. A designer generally shows the correctness of a protocol ny impleme...
Nirav Dave, Man Cheuk Ng, Arvind
CAV
2005
Springer
106views Hardware» more  CAV 2005»
16 years 11 days ago
Incremental Algorithms for Inter-procedural Analysis of Safety Properties
Automaton-based static program analysis has proved to be an effective tool for bug finding. Current tools generally re-analyze a program from scratch in response to a change in t...
Christopher L. Conway, Kedar S. Namjoshi, Dennis D...
CAV
2005
Springer
110views Hardware» more  CAV 2005»
16 years 11 days ago
Extended Weighted Pushdown Systems
Recent work on weighted-pushdown systems shows how to generalize interprocedural-dataflow analysis to answer “stack-qualified queries”, which answer the question “what data...
Akash Lal, Thomas W. Reps, Gogul Balakrishnan
FMCO
2005
Springer
116views Formal Methods» more  FMCO 2005»
16 years 11 days ago
Control of Modular and Distributed Discrete-Event Systems
Control of modular and distributed discrete-event systems appears as an approach to handle computational complexity of synthesizing supervisory controllers for large scale systems....
Jan Komenda, Jan H. van Schuppen
FORMATS
2005
Springer
16 years 11 days ago
Real Time Temporal Logic: Past, Present, Future
This paper attempts to improve our understanding of timed languages and their relation to timed automata. We start by giving a constructive proof of the folk theorem stating that t...
Oded Maler, Dejan Nickovic, Amir Pnueli