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FMCAD
2007
Springer
15 years 10 months ago
Boosting Verification by Automatic Tuning of Decision Procedures
Parameterized heuristics abound in computer aided design and verification, and manual tuning of the respective parameters is difficult and time-consuming. Very recent results from ...
Frank Hutter, Domagoj Babic, Holger H. Hoos, Alan ...
FMCAD
2007
Springer
15 years 10 months ago
Improved Design Debugging Using Maximum Satisfiability
In today's SoC design cycles, debugging is one of the most time consuming manual tasks. CAD solutions strive to reduce the inefficiency of debugging by identifying error sourc...
Sean Safarpour, Hratch Mangassarian, Andreas G. Ve...
FORMATS
2007
Springer
15 years 10 months ago
Partial Order Reduction for Verification of Real-Time Components
Abstract. We describe a partial order reduction technique for a realtime component model. Components are described as timed automata with data ports, which can be composed in stati...
John Håkansson, Paul Pettersson
FMICS
2009
Springer
15 years 10 months ago
Platform-Specific Restrictions on Concurrency in Model Checking of Java Programs
The main limitation of software model checking is that, due to state explosion, it does not scale to real-world multi-threaded programs. One of the reasons is that current software...
Pavel Parizek, Tomás Kalibera
FORMATS
2009
Springer
15 years 10 months ago
Safe Runtime Verification of Real-Time Properties
Abstract. Introducing a monitor on a system typically changes the system's behaviour by slowing the system down and increasing memory consumption. This may possibly result in ...
Christian Colombo, Gordon J. Pace, Gerardo Schneid...