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IPPS
2007
IEEE
16 years 29 days ago
A General Purpose Partially Reconfigurable Processor Simulator (PReProS)
An innovative technique to model and simulate partial and dynamic reconfigurable processors is presented in this paper. The basis for development is a SystemC kernel modified for ...
Alisson Vasconcelos De Brito, Matthias Kühnle...
EEMMAS
2007
Springer
16 years 25 days ago
Engineering Business Ecosystems Using Environment-Mediated Interactions
Abstract The increasingly complex and dynamic nature of contemporary markets demands that a business engages in an ongoing dialogue with all aspects of its environment, including o...
César A. Marín, Iain Duncan Stalker,...
LCN
2003
IEEE
15 years 12 months ago
A holistic methodology for network processor design
The GigaNetIC project aims to develop high-speed components for networking applications based on massively parallel architectures. A central part of this project is the design, ev...
Olaf Bonorden, Nikolaus Brüls, Uwe Kastens, D...
ICCD
1992
IEEE
124views Hardware» more  ICCD 1992»
15 years 10 months ago
The ETCA Data-Flow Functional Computer for Real-Time Image Processing
This paper presents a data- ow computer, constituted of a large array of data- ow processors and programmed using a functional language, and its application to realtime image proc...
Georges Quénot, Bertrand Zavidovique
FPL
2009
Springer
179views Hardware» more  FPL 2009»
15 years 10 months ago
Building heterogeneous reconfigurable systems using threads
Field Programmable Gate Arrays (FPGAs) have long held the promise of allowing designers to create systems with performance levels close to custom circuits but with a software-like...
Jason Agron, David L. Andrews