2088 search results - page 254 / 418 » Formal Approach to Integrating Feature and Architecture Mode... |
152
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DAC
2009
ACM
16 years 7 months ago
2009
ACM
Functional validation of a processor design through execution of a suite of test programs is common industrial practice. In this paper, we develop a high-level architectural speci...
157
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ICCAD
2006
IEEE
16 years 3 months ago
2006
IEEE
With shrinking feature size and growing integration density in the Deep Sub-Micron technologies, the global buses are fast becoming the “weakest-links” in VLSI design. They ha...
210
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FMCAD
2006
Springer
15 years 10 months ago
2006
Springer
The importance of re-usable Intellectual Properties (IPs) cores is increasing due to the growing complexity of today's system-on-chip and the need for rapid prototyping. In th...
162
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DATE
2010
IEEE
15 years 10 months ago
2010
IEEE
-- Starting Electronic System Level (ESL) design flows with executable High-Level Models (HLMs) has the potential to sustainably improve productivity. However, writing good HLMs fo...
143
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SIGSOFT
2005
ACM
16 years 7 months ago
2005
ACM
Fluent model checking is an automated technique for verifying that an event-based operational model satisfies some state-based declarative properties. The link between the event-b...