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VLDB
2004
ACM
126views Database» more  VLDB 2004»
15 years 11 months ago
STEPS towards Cache-resident Transaction Processing
Online transaction processing (OLTP) is a multibillion dollar industry with high-end database servers employing state-of-the-art processors to maximize performance. Unfortunately,...
Stavros Harizopoulos, Anastassia Ailamaki
DAC
2004
ACM
15 years 11 months ago
Area-efficient instruction set synthesis for reconfigurable system-on-chip designs
Silicon compilers are often used in conjunction with Field Programmable Gate Arrays (FPGAs) to deliver flexibility, fast prototyping, and accelerated time-to-market. Many of these...
Philip Brisk, Adam Kaplan, Majid Sarrafzadeh
CODES
1998
IEEE
15 years 10 months ago
Software timing analysis using HW/SW cosimulation and instruction set simulator
Timing analysis for checking satisfaction of constraints is a crucial problem in real-time system design. In some current approaches, the delay of software modules is precalculate...
Jie Liu, Marcello Lajolo, Alberto L. Sangiovanni-V...
ISLPED
2003
ACM
90views Hardware» more  ISLPED 2003»
15 years 11 months ago
Low cost instruction cache designs for tag comparison elimination
Tag comparison elimination (TCE) is an effective approach to reduce I-cache energy. Current research focuses on finding good tradeoffs between hardware cost and percentage of comp...
Youtao Zhang, Jun Yang 0002
ARITH
2005
IEEE
16 years 13 hour ago
Some Functions Computable with a Fused-Mac
The fused multiply accumulate instruction (fused-mac) that is available on some current processors such as the Power PC or the Itanium eases some calculations. We give examples of...
Sylvie Boldo, Jean-Michel Muller