1563 search results - page 286 / 313 » Flexible instruction processors |
183
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DAC
2005
ACM
16 years 7 months ago
2005
ACM
In this paper, we describe FLEXBUS, a flexible, high-performance onchip communication architecture featuring a dynamically configurable topology. FLEXBUS is designed to detect run...
138
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HPCA
2008
IEEE
16 years 6 months ago
2008
IEEE
The interconnect mechanisms (shared bus or crossbar) used in current chip-multiprocessors (CMPs) are expected to become a bottleneck that prevents these architectures from scaling...
173
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IPPS
2005
IEEE
15 years 11 months ago
2005
IEEE
Reconfigurable computing offers the promise of performing computations in hardware to increase performance and efficiency while retaining much of the flexibility of a software sol...
182
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SSDBM
2010
IEEE
15 years 11 months ago
2010
IEEE
Science is becoming data-intensive, requiring new software architectures that can exploit resources at all scales: local GPUs for interactive visualization, server-side multi-core ...
186
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IPPS
1999
IEEE
1999
IEEE
Visualization and Performance Prediction of Multithreaded Solaris Programs by Tracing Kernel Threads
15 years 10 months ago
Efficient performance tuning of parallel programs is often hard. We present a performance prediction and visualization tool called VPPB. Based on a monitored uni-processor executi...