1563 search results - page 242 / 313 » Flexible instruction processors |
181
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EMSOFT
2010
Springer
15 years 4 months ago
2010
Springer
We propose the first polynomial-time code selection algorithm for minimising the worst-case execution time of a nonnested loop executed on a fully pipelined processor that uses sc...
168
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IPPS
2010
IEEE
15 years 4 months ago
2010
IEEE
Abstract--Dictionary-based string matching (DBSM) is a critical component of Deep Packet Inspection (DPI), where thousands of malicious patterns are matched against high-bandwidth ...
174
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ASPLOS
2012
ACM
14 years 2 months ago
2012
ACM
Processor emulators are widely used to provide isolation and instrumentation of binary software. However they have proved difficult to implement correctly: processor specificati...
211
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IWOMP
2007
Springer
16 years 14 days ago
2007
Springer
The Cell processor is a heterogeneous multi-core processor with one Power Processing Engine (PPE) core and eight Synergistic Processing Engine (SPE) cores. Each SPE has a directly...
151
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IEEEPACT
2006
IEEE
16 years 11 days ago
2006
IEEE
Modern out-of-order processors with non-blocking caches exploit Memory-Level Parallelism (MLP) by overlapping cache misses in a wide instruction window. The exploitation of MLP, h...