1563 search results - page 240 / 313 » Flexible instruction processors |
143
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LCPC
2001
Springer
15 years 10 months ago
2001
Springer
Abstract. We describe the structure of a compilation system that generates code for processor architectures supporting both explicit and implicit parallel threads. Such architectur...
147
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HPCA
1998
IEEE
15 years 10 months ago
1998
IEEE
A novel dynamic register renaming approach is proposed in this work. The key idea of the novel scheme is to delay the allocation of physical registers until a late stage in the pi...
186
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ASPLOS
1998
ACM
15 years 10 months ago
1998
ACM
As the gap between memory and processor speeds continues to widen, cache efficiency is an increasingly important component of processor performance. Compiler techniques have been...
180
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ISCA
1997
IEEE
15 years 10 months ago
1997
IEEE
Improvements in main memory speeds have not kept pace with increasing processor clock frequency and improved exploitation of instruction-level parallelism. Consequently, the gap b...
159
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MICRO
1997
IEEE
15 years 10 months ago
1997
IEEE
Predicated execution is a promising architectural feature for exploiting instruction-level parallelism in the presence of control flow. Compiling for predicated execution involve...