Sciweavers

1563 search results - page 238 / 313
» Flexible instruction processors
Sort
View
CASES
2006
ACM
16 years 9 days ago
A case study of multi-threading in the embedded space
The continuing miniaturization of technology coupled with wireless networks has made it feasible to physically embed sensor network systems into the environment. Sensor net proces...
Greg Hoover, Forrest Brewer, Timothy Sherwood
ISLPED
2006
ACM
100views Hardware» more  ISLPED 2006»
16 years 9 days ago
Selective writeback: exploiting transient values for energy-efficiency and performance
Today’s superscalar microprocessors use large, heavily-ported physical register files (RFs) to increase the instruction throughput. The high complexity and power dissipation of ...
Deniz Balkan, Joseph J. Sharkey, Dmitry Ponomarev,...
SAC
2004
ACM
15 years 11 months ago
L0 buffer energy optimization through scheduling and exploration
Clustered L0 buffers are an interesting alternative to reduce energy consumption in the instruction memory hierarchy of embedded VLIW processors. Currently, the synthesis of L0 cl...
Murali Jayapala, Tom Vander Aa, Francisco Barat, G...
EMSOFT
2004
Springer
15 years 11 months ago
An approach for integrating basic retiming and software pipelining
Basic retiming is an algorithm originally developed for hardware optimization. Software pipelining is a technique proposed to increase instruction-level parallelism for parallel p...
Noureddine Chabini, Wayne Wolf
IEEEPACT
2003
IEEE
15 years 11 months ago
Compilation, Architectural Support, and Evaluation of SIMD Graphics Pipeline Programs on a General-Purpose CPU
Graphics and media processing is quickly emerging to become one of the key computing workloads. Programmable graphics processors give designers extra flexibility by running a sma...
Mauricio Breternitz Jr., Herbert H. J. Hum, Sanjee...