1563 search results - page 236 / 313 » Flexible instruction processors |
162
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MICRO
2010
IEEE
15 years 4 months ago
2010
IEEE
Soft error reliability is increasingly becoming a first-order design concern for microprocessors, as a result of higher transistor counts, shrinking device geometries and lowering ...
186
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ICPP
2002
IEEE
15 years 11 months ago
2002
IEEE
A software cache implements instruction and data caching entirely in software. Dynamic binary rewriting offers a means to specialize the software cache miss checks at cache miss t...
162
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HPCA
2008
IEEE
16 years 6 months ago
2008
IEEE
In this paper, we propose Runahead Threads (RaT) as a valuable solution for both reducing resource contention and exploiting memory-level parallelism in Simultaneous Multithreaded...
129
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ICCD
2006
IEEE
16 years 3 months ago
2006
IEEE
Abstract— In this paper, we describe the design and implementation of the primary memory system of the TRIPS processor. To match the aggressive execution bandwidth and support hi...
145
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ICCD
2004
IEEE
16 years 3 months ago
2004
IEEE
Large register file with multiple ports, but with a minimal access time, is a critical component in a superscalar processor. Analysis of the lifetime of a logical to physical reg...