1563 search results - page 232 / 313 » Flexible instruction processors |
168
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IPPS
1996
IEEE
15 years 10 months ago
1996
IEEE
Multiple instruction issue processors place high demands on register file bandwidth. One solution to reduce this bottleneck is the use of multiple register files. Register allocat...
148
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ICPADS
1994
IEEE
15 years 10 months ago
1994
IEEE
: Software cache coherence schemes are very desirable in the design of scalable multiprocessors and massively parallel processors. The authors propose a software cache coherence sc...
175
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ARCS
2006
Springer
15 years 10 months ago
2006
Springer
While trace cache, value prediction, and prefetching have been shown to be effective in the single-threaded superscalar, there has been no analysis of these techniques in a Simulta...
139
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ASPDAC
2001
ACM
15 years 10 months ago
2001
ACM
Abstract-- In order to continue to produce circuits of increasing speeds, designers must consider aggressive circuit design styles such as self-resetting or delayed-reset domino ci...
161
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ASPDAC
2001
ACM
15 years 10 months ago
2001
ACM
Abstract--We present a processor-programmable built-in selftest (BIST) scheme suitable for embedded memory testing in the system-on-a-chip (SOC) environment. The proposed BIST circ...