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ISVLSI
2005
IEEE
157views VLSI» more  ISVLSI 2005»
15 years 12 months ago
Configurable Multiprocessors for High-Performance MPEG-4 Video Coding
We investigate the performance improvement of a multithreaded MPEG-4 video encoder executing on a configurable, extensible, SoC multiprocessor. Architecture-level results indicate...
Vassilios A. Chouliaras, Tom R. Jacobs, Ashwin K. ...
ESA
2004
Springer
166views Algorithms» more  ESA 2004»
15 years 11 months ago
Super Scalar Sample Sort
Sample sort, a generalization of quicksort that partitions the input into many pieces, is known as the best practical comparison based sorting algorithm for distributed memory para...
Peter Sanders, Sebastian Winkel
ESTIMEDIA
2004
Springer
15 years 11 months ago
A queuing-theoretic performance model for context-flow system-on-chip platforms
Abstract—Few analytical performance models that relate performance figure of merit to architectural design decisions are reported in recent studies of network-on-chip, which pre...
Rami Beidas, Jianwen Zhu
DATE
2003
IEEE
86views Hardware» more  DATE 2003»
15 years 11 months ago
Layered, Multi-Threaded, High-Level Performance Design
A primary goal of high-level modeling is to efficiently explore a broad design space, converging on an optimal or near-optimal system architecture before moving to a more detaile...
Andrew S. Cassidy, JoAnn M. Paul, Donald E. Thomas
IEEEINTERACT
2003
IEEE
15 years 11 months ago
Compiler-Directed Resource Management for Active Code Regions
Recent studies on program execution behavior reveal that a large amount of execution time is spent in small frequently executed regions of code. Whereas adaptive cache management ...
Ravikrishnan Sree, Alex Settle, Ian Bratt, Daniel ...