1563 search results - page 228 / 313 » Flexible instruction processors |
157
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ICCD
2003
IEEE
16 years 3 months ago
2003
IEEE
Compiled simulation is a well known technique for improving the performance of instruction set simulators at the cost of compilation time. However the compilation time overhead ma...
165
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CGO
2009
IEEE
16 years 1 months ago
2009
IEEE
The development of high-performance libraries has become extraordinarily difficult due to multiple processor cores, vector instruction sets, and deep memory hierarchies. Often, t...
181
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SEUS
2009
IEEE
16 years 1 months ago
2009
IEEE
Future embedded systems are expected to use chip-multiprocessors to provide the execution power for increasingly demanding applications. Multiprocessors increase the pressure on th...
139
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ARCS
2010
Springer
16 years 25 days ago
2010
Springer
Register renaming is a widely used technique to remove false data dependencies in superscalar datapaths. Rename logic consists of a table that holds a physical register mapping for...
130
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CGO
2008
IEEE
16 years 25 days ago
2008
IEEE
Vector-thread (VT) architectures exploit multiple forms of parallelism simultaneously. This paper describes a compiler for the Scale VT architecture, which takes advantage of the ...