1563 search results - page 223 / 313 » Flexible instruction processors |
148
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MICRO
2002
IEEE
15 years 11 months ago
2002
IEEE
We describe the design, analysis, and performance of an on–line algorithm to dynamically control the frequency/voltage of a Multiple Clock Domain (MCD) microarchitecture. The MC...
159
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RTSS
1999
IEEE
15 years 10 months ago
1999
IEEE
Previous timing analysis methods have assumed that the worst-case instruction execution time necessarily corresponds to the worst-case behavior. We show that this assumption is wr...
187
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ASPLOS
1992
ACM
15 years 10 months ago
1992
ACM
Software-controlled data prefetching is a promising technique for improving the performance of the memory subsystem to match today's high-performance processors. While prefet...
149
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ICS
1989
Tsinghua U.
15 years 10 months ago
1989
Tsinghua U.
Control intensive scalar programs pose a very different challenge to highly pipelined supercomputers than vectorizable numeric applications. Function call/return and branch instru...
183
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ACSC
2004
IEEE
15 years 10 months ago
2004
IEEE
When modern processors keep increasing the instruction window size and the issue width to exploit more instruction-level parallelism (ILP), the demand of larger physical register ...