1563 search results - page 222 / 313 » Flexible instruction processors |
145
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FPL
2007
Springer
16 years 16 days ago
2007
Springer
In this paper, we present a shared instruction and data memory controller for the On-Chip Memory (OCM) bus of the PowerPC embedded in the Virtex-4 chip. The traditional design of ...
157
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ICESS
2007
Springer
16 years 15 days ago
2007
Springer
Over recent years automated face detection and recognition (FDR) have gained significant attention from the commercial and research sectors. This paper presents an embedded face de...
185
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MICRO
2006
IEEE
16 years 11 days ago
2006
IEEE
The superblock is a scheduling region which exposes instruction level parallelism beyond the basic block through speculative execution of instructions. In general, scheduling supe...
160
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ISCAS
2005
IEEE
15 years 12 months ago
2005
IEEE
— Program code size has become a critical design constraint of embedded systems. Large program codes require large memories, which increase the size and cost of the chip. Poor co...
154
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ISCA
2003
IEEE
15 years 11 months ago
2003
IEEE
In a single second a modern processor can execute billions of instructions. Obtaining a bird’s eye view of the behavior of a program at these speeds can be a difficult task whe...