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ASPLOS
2008
ACM
15 years 8 months ago
SoftSig: software-exposed hardware signatures for code analysis and optimization
Many code analysis techniques for optimization, debugging, or parallelization need to perform runtime disambiguation of sets of addresses. Such operations can be supported efficie...
James Tuck, Wonsun Ahn, Luis Ceze, Josep Torrellas
ISCAS
2006
IEEE
154views Hardware» more  ISCAS 2006»
16 years 11 days ago
FleXilicon: a reconfigurable architecture for multimedia and wireless communications
— This paper proposes a new reconfigurable architecture for multi-media and wireless communications. The proposed architecture addresses three critical design issues with the loo...
Jong-Suk Lee, Dong Sam Ha
DATE
2002
IEEE
115views Hardware» more  DATE 2002»
15 years 11 months ago
Design Technology for Networked Reconfigurable FPGA Platforms
Future networked appliances should be able to download new services or upgrades from the network and execute them locally. This flexibility is typically achieved by processors tha...
Steve Guccione, Diederik Verkest, Ivo Bolsens
EDUTAINMENT
2008
Springer
15 years 8 months ago
Efficient Method for Point-Based Rendering on GPUs
Abstract. We describe methods for high-performance and high-quality rendering of point models, including advanced shading, anti-aliasing, and transparency. we keep the rendering qu...
La-mei Yan, You-wei Yuan
WSC
2001
15 years 7 months ago
Use of DaSSF in a scalable multiprocessor wireless simulation architecture
The problem of efficient load distribution and scaling of large-scale wireless communication system simulation on multiprocessor architectures (both shared memory and cluster arra...
Trefor J. Delve, Nathan Smith