Sciweavers

1563 search results - page 211 / 313
» Flexible instruction processors
Sort
View
SC
1992
ACM
15 years 10 months ago
Compiler Code Transformations for Superscalar-Based High Performance Systems
Exploiting parallelism at both the multiprocessor level and the instruction level is an e ective means for supercomputers to achieve high-performance. The amount of instruction-le...
Scott A. Mahlke, William Y. Chen, John C. Gyllenha...
ASPDAC
2000
ACM
109views Hardware» more  ASPDAC 2000»
15 years 10 months ago
A technique for QoS-based system partitioning
Quality of service (QoS) has been an important topic of many research communities. Combined with an advanced and retargetable compiler, variability of applicationsspecific very lar...
Johnson S. Kin, Chunho Lee, William H. Mangione-Sm...
DAC
2005
ACM
15 years 8 months ago
VLIW: a case study of parallelism verification
Parallelism in processor architecture and design imposes a verification challenge as the exponential growth in the number of execution combinations becomes unwieldy. In this paper...
Allon Adir, Yaron Arbetman, Bella Dubrov, Yossi Li...
CGF
2006
198views more  CGF 2006»
15 years 6 months ago
Real-Time Weighted Pose-Space Deformation on the GPU
WPSD (Weighted Pose Space Deformation) is an example based skinning method for articulated body animation. The per-vertex computation required in WPSD can be parallelized in a SIM...
Taehyun Rhee, John P. Lewis, Ulrich Neumann
CORR
2006
Springer
103views Education» more  CORR 2006»
15 years 6 months ago
VXA: A Virtual Architecture for Durable Compressed Archives
Data compression algorithms change frequently, and obsolete decoders do not always run on new hardware and operating systems, threatening the long-term usability of content archiv...
Bryan Ford