1563 search results - page 204 / 313 » Flexible instruction processors |
184
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ISCA
2002
IEEE
15 years 6 months ago
2002
IEEE
Traditional vector architectures have shown to be very effective for regular codes where the compiler can detect data-level parallelism. However, this SIMD parallelism is also pre...
182
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TC
2011
15 years 1 months ago
2011
—This paper considers the problem of dividing a two-word integer by a single-word integer, together with a few extensions and applications. Due to lack of efficient division ins...
179
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SEUS
2009
IEEE
16 years 1 months ago
2009
IEEE
Abstract. In this paper we explore the combination of a time-predictable chipmultiprocessor system with the single-path programming paradigm. Time-sliced arbitration of the main me...
159
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EUROPAR
2007
Springer
16 years 17 days ago
2007
Springer
We describe an approach to automatic parallelisation of programs written in Sieve C++ (Codeplay’s C++ extension), using the Sieve compiler and runtime system. In Sieve C++, the p...
150
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ASAP
1996
IEEE
15 years 10 months ago
1996
IEEE
Kestrel is a programmable linear array processor designed for sequence analysis. Among other features, Kestrel includes an 8-bit word, a single-cycle add-and-minimize instruction, ...