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PDPTA
2007
15 years 7 months ago
Suppressing Independent Loops in Packing/Unpacking Loop Nest to Reduce Message Size for Message-passing Code
- In this paper we experiment with two optimization techniques we are considering implementing in a parallelizing compiler that generates parallel code for a distributed-memory sys...
P. Jerry Martin, Clayton S. Ferner
CATA
2003
15 years 7 months ago
Implementation and Performance Evaluation of Intel VTUNE Image Processing Functions in the MATLAB Environment
Many current general purpose processors use extensions to the instruction set architecture to enhance the performance of digital image processing and multimedia applications. In t...
Phaisit Chewputtanagul, David Jeff Jackson, Kennet...
CASCON
1996
118views Education» more  CASCON 1996»
15 years 7 months ago
Automatic parallelization for symmetric shared-memory multiprocessors
The trend in workstation hardware is towards symmetric shared-memory multiprocessors (SMPs). User expectations are for (largely) automatic exploitation of parallelismon an SMP, si...
Jyh-Herng Chow, Leonard E. Lyon, Vivek Sarkar
FAC
2000
124views more  FAC 2000»
15 years 6 months ago
Algebraic Models of Correctness for Microprocessors
In this paper we present a method of describing microprocessors at different levels of temporal and data abstraction. We consider microprogrammed, pipelined and superscalar proces...
Anthony C. J. Fox, Neal A. Harman
CODES
2006
IEEE
16 years 14 days ago
A multiprocessing approach to accelerate retargetable and portable dynamic-compiled instruction-set simulation
Traditionally, instruction-set simulators (ISS’s) are sequential programs running on individual processors. Besides the advances of simulation techniques, ISS’s have been main...
Wei Qin, Joseph D'Errico, Xinping Zhu