1563 search results - page 201 / 313 » Flexible instruction processors |
159
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BIRTHDAY
2006
Springer
15 years 10 months ago
2006
Springer
We describe a gate level design of a FlexRay-like bus interface. An electronic control unit (ECU) is obtained by integrating this interface into the design of the verified VAMP pro...
203
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DDECS
2006
IEEE
15 years 10 months ago
2006
IEEE
Abstract-- Hard real-time systems need methods to determine upper bounds for their execution times, usually called worst-case execution times. Timing anomalies are counterintuitive...
196
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DAC
1997
ACM
15 years 10 months ago
1997
ACM
Abstract. Many modern systems are designed as a set of interconnected reactive subsystems. The subsystem verification task is to verify an implementation of the subsystem against t...
182
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DFT
2008
IEEE
15 years 8 months ago
2008
IEEE
This paper presents a concurrent error detection technique for the control logic of a modern microprocessor. Our method is based on execution time prediction for each instruction ...
179
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DSN
2008
IEEE
15 years 8 months ago
2008
IEEE
CMOS technology trends are leading to an increasing incidence of hard (permanent) faults in processors. These faults may be introduced at fabrication or occur in the field. Wherea...