1563 search results - page 197 / 313 » Flexible instruction processors |
171
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MICRO
1997
IEEE
15 years 10 months ago
1997
IEEE
We describe Dead Value Information (DVI) and introduce three new optimizations which exploit it. DVI provides assertions that certain register values are dead, meaning they will n...
151
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WOTUG
2007
15 years 7 months ago
2007
Abstract. The advent of mass-market multicore processors provides exciting new opportunities for parallelism on the desktop. The original C++CSP – a library providing concurrency...
195
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ISCA
2011
IEEE
14 years 10 months ago
2011
IEEE
Conventional high-performance processors utilize register renaming and complex broadcast-based scheduling logic to steer instructions into a small number of heavily-pipelined exec...
150
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IPPS
2002
IEEE
15 years 11 months ago
2002
IEEE
In a paper presented last year at WMPP’01 [Walker01], we described the initial prototype of an associative processor implemented using field-programmable logic devices (FPLDs). ...
159
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FPL
2009
Springer
15 years 11 months ago
2009
Springer
Commercial soft processors are unable to effectively exploit the data parallelism present in many embedded systems workloads, requiring FPGA designers to exploit it (laboriously) ...