Sciweavers

1563 search results - page 196 / 313
» Flexible instruction processors
Sort
View
ISCA
2005
IEEE
166views Hardware» more  ISCA 2005»
16 years 3 hour ago
Increased Scalability and Power Efficiency by Using Multiple Speed Pipelines
One of the most important problems faced by microarchitecture designers is the poor scalability of some of the current solutions with increased clock frequencies and wider pipelin...
Emil Talpes, Diana Marculescu
IPPS
2002
IEEE
15 years 11 months ago
Hierarchical Interconnects for On-Chip Clustering
In the sub-micron technology era, wire delays are becoming much more important than gate delays, making it particularly attractive to go for clustered designs. A common form of cl...
Aneesh Aggarwal, Manoj Franklin
CSIE
2009
IEEE
15 years 11 months ago
K-Means on Commodity GPUs with CUDA
K-means algorithm is one of the most famous unsupervised clustering algorithms. Many theoretical improvements for the performance of original algorithms have been put forward, whi...
Hong-tao Bai, Li-li He, Dan-tong Ouyang, Zhan-shan...
MICRO
2000
IEEE
80views Hardware» more  MICRO 2000»
15 years 10 months ago
Silent stores for free
Silent store instructions write values that exactly match the values that are already stored at the memory address that is being written. A recent study reveals that significant ...
Kevin M. Lepak, Mikko H. Lipasti
ISCA
1999
IEEE
94views Hardware» more  ISCA 1999»
15 years 10 months ago
Storageless Value Prediction Using Prior Register Values
This paper presents a technique called register value prediction (RVP) which uses a type of locality called register-value reuse. By predicting that an instruction will produce th...
Dean M. Tullsen, John S. Seng