1563 search results - page 193 / 313 » Flexible instruction processors |
162
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VLSISP
1998
15 years 6 months ago
1998
This paper describes the architecture and the performance of a new programmable 16-bit Digital Signal Processor (DSP) engine. It is developed specifically for next generation wire...
195
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CIKM
2011
Springer
14 years 6 months ago
2011
Springer
Powerful SIMD instructions in modern processors offer an opportunity for greater search performance. In this paper, we apply these instructions to decoding search engine posting ...
140
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HPCA
2005
IEEE
16 years 6 months ago
2005
IEEE
Due to increasing power densities, both on-chip average and peak temperatures are fast becoming a serious bottleneck in processor design. This is due to the cost of removing the h...
143
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ASPLOS
2006
ACM
16 years 11 days ago
2006
ACM
Cycles per Instruction (CPI) stacks break down processor execution time into a baseline CPI plus a number of miss event CPI components. CPI breakdowns can be very helpful in gaini...
175
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INFOCOM
2002
IEEE
15 years 11 months ago
2002
IEEE
—To provide flexibility in deploying new protocols and services, general-purpose processing engines are being placed in the datapath of routers. Such network processors are typi...