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ICCD
2006
IEEE
103views Hardware» more  ICCD 2006»
16 years 3 months ago
Architectural Support for Run-Time Validation of Control Flow Transfer
—Current micro-architecture blindly uses the address in the program counter to fetch and execute instructions without validating its legitimacy. Whenever this blind-folded instru...
Yixin Shi, Sean Dempsey, Gyungho Lee
ICCD
2003
IEEE
111views Hardware» more  ICCD 2003»
16 years 3 months ago
Routed Inter-ALU Networks for ILP Scalability and Performance
Modern processors rely heavily on broadcast networks to bypass instruction results to dependent instructions in the pipeline. However, as clock rates increase, architectures get w...
Karthikeyan Sankaralingam, Vincent Ajay Singh, Ste...
SBACPAD
2009
IEEE
155views Hardware» more  SBACPAD 2009»
16 years 1 months ago
SPARC16: A New Compression Approach for the SPARC Architecture
RISC processors can be used to face the ever increasing demand for performance required by embedded systems. Nevertheless, this solution comes with the cost of poor code density. ...
Leonardo Luiz Ecco, Bruno Cardoso Lopes, Eduardo C...
ISCA
2005
IEEE
118views Hardware» more  ISCA 2005»
16 years 9 hour ago
Continuous Optimization
This paper presents a hardware-based dynamic optimizer that continuously optimizes an application’s instruction stream. In continuous optimization, dataflow optimizations are p...
Brian Fahs, Todd M. Rafacz, Sanjay J. Patel, Steve...
IH
2005
Springer
15 years 12 months ago
Data Hiding in Compiled Program Binaries for Enhancing Computer System Performance
Abstract. Information hiding has been studied in many security applications such as authentication, copyright management and digital forensics. In this work, we introduce a new app...
Ashwin Swaminathan, Yinian Mao, Min Wu, Krishnan K...