1563 search results - page 189 / 313 » Flexible instruction processors |
174
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ISCA
2006
IEEE
15 years 6 months ago
2006
IEEE
Conventional relaxed memory ordering techniques follow a proactive model: at a synchronization point, a processor makes its own updates to memory available to other processors by ...
175
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DAC
2003
ACM
16 years 7 months ago
2003
ACM
A binary decoder is a common component of software development tools such as instruction set simulators, disassemblers and debuggers. The efficiency of the decoder can have a sign...
189
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FCCM
2002
IEEE
15 years 11 months ago
2002
IEEE
The paper presents a Design Space Exploration (DSE) experiment which has been carried out in order to determine the optimum FPGA–based Variable-Length Decoder (VLD) computing re...
180
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CF
2005
ACM
15 years 8 months ago
2005
ACM
This paper evaluates how much extended dictionary-based code compression techniques can reduce the static code size. In their simplest form, such methods statically identify ident...
192
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ISCAPDCS
2007
15 years 7 months ago
2007
— Next generation multimedia mobile phones that use the high bandwidth 3G cellular radio network consume more power. Multimedia algorithms such as speech, video transcodecs have ...