1563 search results - page 187 / 313 » Flexible instruction processors |
168
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DATE
2003
IEEE
15 years 11 months ago
2003
IEEE
Novel reconfigurable computing architectures exploit the inherent parallelism available in many signalprocessing problems. These architectures often consist of networks of compute...
126
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MICRO
2003
IEEE
15 years 11 months ago
2003
IEEE
The physical register file is an important component of a dynamically-scheduled processor. Increasing the amount of parallelism places increasing demands on the physical register...
148
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IPPS
2000
IEEE
15 years 10 months ago
2000
IEEE
This paper presents a new methodology for implementing fast synchronization on scalable cache-coherent multiprocessors, through the use of hybrid primitives. Hybrid primitives lev...
199
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DSD
2008
IEEE
15 years 8 months ago
2008
IEEE
We evaluate the leakage reduction for both instruction and data cache in presence of drowsy or decay techniques. We discovered that a filter cache, traditionally used for reducing...
165
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CSREAESA
2006
15 years 7 months ago
2006
Transport triggered architecture (TTA) has been shown to provide an efficient way to design application specific instruction set processors. However, the interconnection network of...