1563 search results - page 183 / 313 » Flexible instruction processors |
187
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ISCA
1996
IEEE
15 years 10 months ago
1996
IEEE
Memory latency is an important bottleneck in system performance that cannot be adequately solved by hardware alone. Several promising software techniques have been shown to addres...
155
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INFOCOM
2007
IEEE
16 years 22 days ago
2007
IEEE
Next-generation high-end Network Processors (NP) must address demands from both diversified applications and ever-increasing traffic pressure. One major challenge is to design an e...
164
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CF
2004
ACM
15 years 12 months ago
2004
ACM
The ever increasing gap between processor and memory speed, sometimes referred to as the Memory Wall problem [42], has a very negative impact on performance. This mismatch will be...
157
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CASES
2006
ACM
16 years 12 days ago
2006
ACM
This paper considers the efficient parallel implementation of control constructs and expressions written in a common software programming language and synthesised to FPGA platform...
166
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LCTRTS
2005
Springer
15 years 12 months ago
2005
Springer
Efficient implementation of DSP applications is critical for many embedded systems. Optimising C compilers for embedded processors largely focus on code generation and instructio...