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IEEEPACT
1999
IEEE
15 years 10 months ago
A Cost-Effective Clustered Architecture
In current superscalar processors, all floating-point resources are idle during the execution of integer programs. As previous works show, this problem can be alleviated if the fl...
Ramon Canal, Joan-Manuel Parcerisa, Antonio Gonz&a...
ISSS
1999
IEEE
131views Hardware» more  ISSS 1999»
15 years 10 months ago
Compressed Code Execution on DSP Architectures
Decreasing the program size has become an important goal in the design of embedded systems target to mass production. This problem has led to a number of efforts aimed at designin...
Paulo Centoducatte, Ricardo Pannain, Guido Araujo
ISCA
1998
IEEE
119views Hardware» more  ISCA 1998»
15 years 10 months ago
Execution Characteristics of Desktop Applications on Windows NT
This paper examines the performance of desktop applications running on the Microsoft Windows NT operating system on Intel x86 processors, and contrasts these applications to the p...
Dennis C. Lee, Patrick Crowley, Jean-Loup Baer, Th...
HPCA
2003
IEEE
16 years 6 months ago
Dynamic Data Dependence Tracking and its Application to Branch Prediction
To continue to improve processor performance, microarchitects seek to increase the effective instruction level parallelism (ILP) that can be exploited in applications. A fundament...
Lei Chen, Steve Dropsho, David H. Albonesi
ICCD
2006
IEEE
109views Hardware» more  ICCD 2006»
16 years 3 months ago
Improving Scalability and Complexity of Dynamic Scheduler through Wakeup-Based Scheduling
This paper presents a new scheduling technique to improve the speed, power, and scalability of a dynamic scheduler. In a high-performance superscalar processor, the instruction sc...
Kuo-Su Hsiao, Chung-Ho Chen