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IPPS
1996
IEEE
15 years 10 months ago
Exploiting the Capabilities of Communications Co-Processors
Communications co-processors (CCPs) have become commonplace in modern MPPs and networks of workstations. These co-processors provide dedicated hardware support for fast communicat...
Klaus E. Schauser, Chris J. Scheiman, J. Mitchell ...
DAC
2005
ACM
15 years 8 months ago
Smart diagnostics for configurable processor verification
This paper describes a novel technique called Embedded Test-bench Control (ETC), extensively used in the verification of Tensilica’s latest configurable processor. Conventional ...
Sadik Ezer, Scott Johnson
FPL
2008
Springer
119views Hardware» more  FPL 2008»
15 years 8 months ago
An FPGA-based high-speed, low-latency trigger processor for high-energy physics
An example of an FPGA based application for a high-energy physics experiment is presented which features all facets of modern FPGA design. The special requirements here are high b...
Jan de Cuveland, Felix Rettig, Venelin Angelov, Vo...
ANCS
2009
ACM
15 years 4 months ago
EINIC: an architecture for high bandwidth network I/O on multi-core processors
This paper proposes a new server architecture EINIC (Enhanced Integrated NIC) for multi-core processors to tackle the mismatch between network speed and host computational capacit...
Guangdeng Liao, Laxmi N. Bhuyan, Danhua Guo, Steve...
VLSID
2003
IEEE
183views VLSI» more  VLSID 2003»
16 years 6 months ago
Design of a 2D DCT/IDCT application specific VLIW processor supporting scaled and sub-sampled blocks
We present an innovative design of an accurate, 2D DCT IDCT processor, which handles scaled and sub-sampled input blocks efficiently. In the IDCT mode, the latency of the processo...
Rohini Krishnan, Om Prakash Gangwal, Jos T. J. van...