1563 search results - page 162 / 313 » Flexible instruction processors |
151
click to vote
SAMOS
2005
Springer
15 years 12 months ago
2005
Springer
In this paper, we introduce the concept of flux caches envisioned to improve processor performance by dynamically changing the cache organization and implementation. Contrary to t...
185
click to vote
ICS
2001
Tsinghua U.
15 years 11 months ago
2001
Tsinghua U.
The issue logic of dynamically scheduled superscalar processors is one of their most complex and power-consuming parts. In this paper we present alternative issue-logic designs th...
128
click to vote
BTW
2009
Springer
15 years 9 months ago
2009
Springer
: BLINK is a prototype of an in-memory based query processor that exploits heavily the underlying CPU infrastructure. It is very sensitive to the processor’s caches and instructi...
173
click to vote
PPSC
1997
15 years 7 months ago
1997
Sparse matrix-vector multiplication is an important kernel that often runs inefficiently on superscalar RISC processors. This paper describes techniques that increase instruction-...
162
click to vote
ASPDAC
2001
ACM
15 years 10 months ago
2001
ACM
Hardware/software partitioning is one of the key processes in a hardware/software cosynthesis system for digital signal processor cores. In hardware/software partitioning, area and...