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IPPS
2006
IEEE
16 years 15 days ago
A code motion technique for accelerating general-purpose computation on the GPU
Recently, graphics processing units (GPUs) are providing increasingly higher performance with programmable internal processors, namely vertex processors (VPs) and fragment process...
T. Ikeda, Fumihiko Ino, Kenichi Hagihara
LCPC
2004
Springer
15 years 12 months ago
Branch Strategies to Optimize Decision Trees for Wide-Issue Architectures
Abstract. Branch predictors are associated with critical design issues for nowadays instruction greedy processors. We study two important domains where the optimization of decision...
Patrick Carribault, Christophe Lemuet, Jean-Thomas...
ICCD
2000
IEEE
159views Hardware» more  ICCD 2000»
15 years 11 months ago
Evaluating Signal Processing and Multimedia Applications on SIMD, VLIW and Superscalar Architectures
This paper aims to provide a quantitative understanding of the performance of DSP and multimedia applications on very long instruction word (VLIW), single instruction multiple dat...
Deependra Talla, Lizy Kurian John, Viktor S. Lapin...
MICRO
1997
IEEE
108views Hardware» more  MICRO 1997»
15 years 10 months ago
Improving the Accuracy and Performance of Memory Communication Through Renaming
As processors continue to exploit more instruction level parallelism, a greater demand is placed on reducing the e ects of memory access latency. In this paper, we introduce a nov...
Gary S. Tyson, Todd M. Austin
APCSAC
2004
IEEE
15 years 10 months ago
A Compiler-Assisted On-Chip Assigned-Signature Control Flow Checking
As device sizes continue shrinking, lower charges are needed to activate gates, and consequently ever smaller external events (such as single ionizing particles of naturally occurr...
Xiaobin Li, Jean-Luc Gaudiot