1563 search results - page 157 / 313 » Flexible instruction processors |
171
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IPPS
2006
IEEE
16 years 15 days ago
2006
IEEE
The earliest-deadline-first (EDF) scheduling of a sporadic real-time task system on a multiprocessor may require that the total utilization of the task system, Usum, not exceed (...
169
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DATE
2008
IEEE
16 years 28 days ago
2008
IEEE
Efficient use of the memory hierarchy is critical for achieving high performance in a multiprocessor systemon-chip. An external memory that is shared between processors is a bottl...
152
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DATE
2006
IEEE
16 years 16 days ago
2006
IEEE
This paper presents the Block Processing Engine (BPE), an Application Specific Instruction-Set Processor (ASIP) explicitly designed for the implementation of multistandard wireles...
170
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CC
2000
Springer
15 years 6 months ago
2000
Springer
The performance of a Java Virtual Machine (JVM) interpreter running on a very long instruction word (VLIW) processor can be improved by means of pipelining. While one bytecode is i...
166
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DAC
2002
ACM
16 years 7 months ago
2002
ACM
In the last decade, instruction-set simulators have become an essential development tool for the design of new programmable architectures. Consequently, the simulator performance ...