1563 search results - page 155 / 313 » Flexible instruction processors |
194
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ISCAPDCS
2001
15 years 7 months ago
2001
This paper presents the evaluation of a non-blocking, decoupled memory/execution, multithreaded architecture known as the Scheduled Dataflow (SDF). The major recent trend in digit...
153
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HPCA
2008
IEEE
16 years 6 months ago
2008
IEEE
Fetch gating mechanisms have been proposed to gate the processor pipeline to reduce the wasted energy consumption due to wrongpath (i.e. mis-speculated) instructions. These scheme...
171
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TC
2002
15 years 6 months ago
2002
Value prediction is a technique that breaks true data dependences by predicting the outcome of an instruction and speculatively executes its data-dependent instructions based on th...
191
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TCAD
2002
15 years 6 months ago
2002
In this paper, an instruction-level energy model is proposed for the data-path of very long instruction word (VLIW) pipelined processors that can be used to provide accurate power ...
170
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DSD
2007
IEEE
16 years 25 days ago
2007
IEEE
Today energy is an important factor in designing a multiprocessor system. The overall goal of this work is to propose a methodology for design space exploration of VLIW multiproce...