1563 search results - page 153 / 313 » Flexible instruction processors |
139
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ISCAS
2006
IEEE
16 years 15 days ago
2006
IEEE
—This paper describes a low cost, low power, versatile computation module that can be used as a coarse-grain building block in multimedia processors. The module, which has a data...
164
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ATS
2003
IEEE
15 years 10 months ago
2003
IEEE
We propose an embedded processor-based built-in self-repair (BISR) design for embedded memories. In the proposed design we reuse the embedded processor that can be found on almost...
159
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ISCA
2005
IEEE
16 years 2 days ago
2005
IEEE
Runahead execution is a technique that improves processor performance by pre-executing the running application instead of stalling the processor when a long-latency cache miss occ...
225
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HPCA
2012
IEEE
14 years 2 months ago
2012
IEEE
Since the onset of pipelined processors, balancing the delay of the microarchitectural pipeline stages such that each microarchitectural pipeline stage has an equal delay has been...
149
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IPPS
2000
IEEE
15 years 11 months ago
2000
IEEE
In a machine that follows the dynamically trace scheduled VLIW (DTSVLIW) architecture, VLIW instructions are built dynamically through an algorithm that can be implemented in hard...