Sciweavers

1563 search results - page 151 / 313
» Flexible instruction processors
Sort
View
DAMON
2009
Springer
16 years 1 months ago
Frequent itemset mining on graphics processors
We present two efficient Apriori implementations of Frequent Itemset Mining (FIM) that utilize new-generation graphics processing units (GPUs). Our implementations take advantage ...
Wenbin Fang, Mian Lu, Xiangye Xiao, Bingsheng He, ...
HOTOS
2003
IEEE
15 years 11 months ago
Certifying Program Execution with Secure Processors
Cerium is a trusted computing architecture that protects a program’s execution from being tampered while the program is running. Cerium uses a physically tamperresistant CPU and...
Benjie Chen, Robert Morris
PLDI
1999
ACM
15 years 10 months ago
Enhanced Code Compression for Embedded RISC Processors
This paper explores compiler techniques for reducing the memory needed to load and run program executables. In embedded systems, where economic incentives to reduce both ram and r...
Keith D. Cooper, Nathaniel McIntosh
JVM
2004
103views Education» more  JVM 2004»
15 years 7 months ago
The Virtual Processor: Fast, Architecture-Neutral Dynamic Code Generation
Tools supporting dynamic code generation tend too be low-level (leaving much work to the client application) or too intimately related with the language/system in which they are u...
Ian Piumarta
ICC
2009
IEEE
116views Communications» more  ICC 2009»
15 years 4 months ago
Efficient Implementation of Binary Sequence Generator for WiMAX and WRAN on Programmable Digital Signal Processor
In this paper, an efficient design for implementing binary sequence generator on 32-bit instruction execution mode TI TMS320C6416 DSP is presented. The main goal is to achieve high...
Lok Tiing Tie, Ser Wah Oh, K. J. M. Kua