1563 search results - page 150 / 313 » Flexible instruction processors |
180
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HPCA
2012
IEEE
14 years 2 months ago
2012
IEEE
Multiprocessor architectures that continuously execute atomic blocks (or chunks) of instructions can improve performance and software productivity. However, all of the prior propo...
153
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HPCA
2003
IEEE
16 years 6 months ago
2003
IEEE
Due to cost, time, and flexibility constraints, simulators are often used to explore the design space when developing a new processor architecture, as well as when evaluating the ...
150
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ASPLOS
2006
ACM
16 years 14 days ago
2006
ACM
Current taint checking architectures monitor tainted data usage mainly with control transfer instructions. An alarm is raised once the program counter becomes tainted. However, su...
198
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CGO
2003
IEEE
15 years 11 months ago
2003
IEEE
A dynamic binary translation system for a co-designed virtual machine is described and evaluated. The underlying hardware directly executes an accumulator-oriented instruction set...
155
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MICRO
1995
IEEE
15 years 10 months ago
1995
IEEE
Untolerated load instruction latencies often have a significant impact on overall program performance. As one means of mitigating this effect, we present an aggressive hardware-b...