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WMPI
2004
ACM
15 years 12 months ago
Scalable cache memory design for large-scale SMT architectures
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past dec...
Muhamed F. Mudawar
ICCD
1999
IEEE
110views Hardware» more  ICCD 1999»
15 years 10 months ago
TriMedia CPU64 Architecture
We present a new VLIW core as a successor to the TriMedia TM1000. The processor is targeted for embedded use in media-processing devices like DTVs and set-top boxes. Intended as a...
Jos T. J. van Eijndhoven, Kees A. Vissers, Evert-J...
ICS
2001
Tsinghua U.
15 years 11 months ago
Slice-processors: an implementation of operation-based prediction
We describe the Slice Processor micro-architecture that implements a generalized operation-based prefetching mechanism. Operation-based prefetchers predict the series of operation...
Andreas Moshovos, Dionisios N. Pnevmatikatos, Amir...
AIED
2009
Springer
15 years 11 months ago
EAGLE: An Intelligent Tutoring System to Support Experiential Learning Through Video Games
EAGLE (Electronic Assistant for Game-Based Learning Experiences) is an intelligent tutoring system that supports learning with video games. We describe how a flexible ontology-base...
Laura Naismith, Emmanuel G. Blanchard, John Ranell...
BIOADIT
2006
Springer
15 years 10 months ago
MOVE Processors That Self-replicate and Differentiate
Abstract. This article describes an implementation of a basic multiprocessor system that exhibits replication and differentiation abilities on the POEtic tissue, a programmable har...
Joël Rossier, Yann Thoma, Pierre-André...