The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past dec...
We present a new VLIW core as a successor to the TriMedia TM1000. The processor is targeted for embedded use in media-processing devices like DTVs and set-top boxes. Intended as a...
Jos T. J. van Eijndhoven, Kees A. Vissers, Evert-J...
We describe the Slice Processor micro-architecture that implements a generalized operation-based prefetching mechanism. Operation-based prefetchers predict the series of operation...
Andreas Moshovos, Dionisios N. Pnevmatikatos, Amir...
EAGLE (Electronic Assistant for Game-Based Learning Experiences) is an intelligent tutoring system that supports learning with video games. We describe how a flexible ontology-base...
Laura Naismith, Emmanuel G. Blanchard, John Ranell...
Abstract. This article describes an implementation of a basic multiprocessor system that exhibits replication and differentiation abilities on the POEtic tissue, a programmable har...