Sciweavers

1563 search results - page 136 / 313
» Flexible instruction processors
Sort
View
HPCA
2009
IEEE
16 years 7 months ago
Bridging the computation gap between programmable processors and hardwired accelerators
New media and signal processing applications demand ever higher performance while operating within the tight power constraints of mobile devices. A range of hardware implementatio...
Kevin Fan, Manjunath Kudlur, Ganesh S. Dasika, Sco...
ICCD
2006
IEEE
97views Hardware» more  ICCD 2006»
16 years 3 months ago
Pesticide: Using SMT Processors to Improve Performance of Pointer Bug Detection
Pointer bugs associated with dynamically-allocated objects resulting in out-of-bounds memory access are an important class of software bugs. Because such bugs cannot be detected e...
Jin-Yi Wang, Yen-Shiang Shue, T. N. Vijaykumar, Sa...
ISCA
2007
IEEE
110views Hardware» more  ISCA 2007»
16 years 24 days ago
Late-binding: enabling unordered load-store queues
Conventional load/store queues (LSQs) are an impediment to both power-efficient execution in superscalar processors and scaling to large-window designs. In this paper, we propose...
Simha Sethumadhavan, Franziska Roesner, Joel S. Em...
ASAP
2003
IEEE
124views Hardware» more  ASAP 2003»
15 years 11 months ago
Arbitrary Bit Permutations in One or Two Cycles
Symmetric-key block ciphers encrypt data, providing data confidentiality over the public Internet. For inter-operability reasons, it is desirable to support a variety of symmetric...
Zhijie Shi, Xiao Yang, Ruby B. Lee
MICRO
2006
IEEE
105views Hardware» more  MICRO 2006»
16 years 16 days ago
Distributed Microarchitectural Protocols in the TRIPS Prototype Processor
Growing on-chip wire delays will cause many future microarchitectures to be distributed, in which hardware resources within a single processor become nodes on one or more switched...
Karthikeyan Sankaralingam, Ramadass Nagarajan, Rob...