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HPCA
2001
IEEE
16 years 6 months ago
CARS: A New Code Generation Framework for Clustered ILP Processors
Clustered ILP processors are characterized by a large number of non-centralized on-chip resources grouped into clusters. Traditional code generation schemes for these processors c...
Krishnan Kailas, Kemal Ebcioglu, Ashok K. Agrawala
ASPLOS
2011
ACM
14 years 10 months ago
Inter-core prefetching for multicore processors using migrating helper threads
Multicore processors have become ubiquitous in today’s systems, but exploiting the parallelism they offer remains difficult, especially for legacy application and applications ...
Md Kamruzzaman, Steven Swanson, Dean M. Tullsen
LCN
2003
IEEE
15 years 11 months ago
Implementation of Resilient Packet Ring Nodes Using Network Processors
Network processors offer a new flexibility for network applications and reduce the time to market for data processing systems. In this paper, we describe the changed development p...
Andreas Kirstädter, Axel Hof, Walter Meyer, E...
HPCA
1999
IEEE
15 years 10 months ago
Dynamically Exploiting Narrow Width Operands to Improve Processor Power and Performance
In general-purpose microprocessors, recent trends have pushed towards 64-bit word widths, primarily to accommodate the large addressing needs of some programs. Many integer proble...
David Brooks, Margaret Martonosi
ISCA
1995
IEEE
92views Hardware» more  ISCA 1995»
15 years 10 months ago
A Comparison of Full and Partial Predicated Execution Support for ILP Processors
One can e ectively utilize predicated execution to improve branch handling in instruction-level parallel processors. Although the potential bene ts of predicated execution are hig...
Scott A. Mahlke, Richard E. Hank, James E. McCormi...