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FCCM
2006
IEEE
125views VLSI» more  FCCM 2006»
16 years 17 days ago
A Multithreaded Soft Processor for SoPC Area Reduction
The growth in size and performance of Field Programmable Gate Arrays (FPGAs) has compelled System-on-aProgrammable-Chip (SoPC) designers to use soft processors for controlling sys...
Blair Fort, Davor Capalija, Zvonko G. Vranesic, St...
IPPS
2002
IEEE
15 years 11 months ago
Eclipse: Heterogeneous Multiprocessor Architecture for Flexible Media Processing
Eclipse is a heterogeneous multiprocessor architecture for high-performance media processing, including highdefinition MPEG encoding/decoding. The scalable architecture framework ...
Martijn J. Rutten, Jos T. J. van Eijndhoven, Evert...
CHES
1999
Springer
91views Cryptology» more  CHES 1999»
15 years 10 months ago
A High-Performance Flexible Architecture for Cryptography
Cryptographic algorithms are more efficiently implemented in custom hardware than in software running on general-purpose processors. However, systems which use hardware implementat...
R. Reed Taylor, Seth Copen Goldstein
RECONFIG
2008
IEEE
122views VLSI» more  RECONFIG 2008»
16 years 27 days ago
Using a CSP Based Programming Model for Reconfigurable Processor Arrays
The growing trend towards adoption of flexible and heterogeneous, parallel computing architectures has increased the challenges faced by the programming community. We propose a me...
Zain-ul-Abdin, Bertil Svensson
DAC
1996
ACM
15 years 10 months ago
Innovative Verification Strategy Reduces Design Cycle Time for High-End Sparc Processor
Superscalar processor developers are creatively leveraging best-in-class design verification tools to meet narrow market windows. Accelerated simulation is especially useful owing...
Val Popescu, Bill McNamara