1563 search results - page 130 / 313 » Flexible instruction processors |
185
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FPL
2004
Springer
15 years 12 months ago
2004
Springer
ASIPs and reconfigurable processors are architectural choices to extend the capabilities of a given processor. ASIPs suffer from fixed hardware after design, while ASIPs and reconf...
149
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ICT
2004
Springer
15 years 12 months ago
2004
Springer
The Resilient Packet Ring IEEE 802.17 is an evolving standard for the construction of Local and Metropolitan Area Networks. The RPR protocol scales to the demands of future packet ...
151
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IPPS
1999
IEEE
15 years 10 months ago
1999
IEEE
Clustering and scheduling of tasks for parallel implementation is a well researched problem. Several techniques have been presented in the literature to improve performance and re...
150
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CASES
2007
ACM
15 years 10 months ago
2007
ACM
The development of robust and efficient synthesis tools is important if asynchronous design is to gain more widespread acceptance. Syntax-directed translation is a powerful synthe...
194
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ERSA
2008
15 years 8 months ago
2008
Coarse-grained dynamically reconfigurable processor arrays (DRPAs) have been received an attention as a flexible and efficient off-loading engine for various types of System-on-Ch...