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ICCD
2000
IEEE
93views Hardware» more  ICCD 2000»
16 years 3 months ago
Cheap Out-of-Order Execution Using Delayed Issue
In superscalar architectures, out-of-order issue mechanisms increase performance by dynamically rescheduling instructions that cannot be statically reordered by the compiler. Whil...
J. P. Grossman
MICRO
2003
IEEE
101views Hardware» more  MICRO 2003»
15 years 11 months ago
Macro-op Scheduling: Relaxing Scheduling Loop Constraints
Ensuring back-to-back execution of dependent instructions in a conventional out-of-order processor requires scheduling logic that wakes up and selects instructions at the same rat...
Ilhyun Kim, Mikko H. Lipasti
MICRO
2000
IEEE
107views Hardware» more  MICRO 2000»
15 years 10 months ago
Register integration: a simple and efficient implementation of squash reuse
Register integration (or simply integration) is a mechanism for incorporating speculative results directly into a sequential execution using data-dependence relationships. In this...
Amir Roth, Gurindar S. Sohi
EGH
2004
Springer
15 years 12 months ago
Mio: fast multipass partitioning via priority-based instruction scheduling
Real-time graphics hardware continues to offer improved resources for programmable vertex and fragment shaders. However, shader programmers continue to write shaders that require ...
Andrew Riffel, Aaron E. Lefohn, Kiril Vidimce, Mar...
ISLPED
2000
ACM
68views Hardware» more  ISLPED 2000»
15 years 11 months ago
Speeding up power estimation of embedded software
Power is increasingly becoming a design constraint for embedded systems. A processor is responsible for energy consumption on account of the software component of the embedded sys...
Akshaye Sama, J. F. M. Theeuwen, M. Balakrishnan