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DAC
2010
ACM
15 years 6 months ago
Instruction cache locking using temporal reuse profile
The performance of most embedded systems is critically dependent on the average memory access latency. Improving the cache hit rate can have significant positive impact on the per...
Yun Liang, Tulika Mitra
IPPS
2005
IEEE
16 years 3 days ago
Technology-based Architectural Analysis of Operand Bypass Networks for Efficient Operand Transport
As semiconductor feature sizes decrease, interconnect delay is becoming a dominant component of processor cycle times. This creates a critical need to shift microarchitectural des...
Hongkyu Kim, D. Scott Wills, Linda M. Wills
COMPCON
1996
IEEE
15 years 10 months ago
Broadband Algorithms with the MicroUnity MediaProcessor
An important objective of the MicroUnity mediaprocessor is to allow the design of systems that replace hardwired functionality with software. One of the key design techniques that...
Curtis Abbott, Henry Massalin, Kevin Peterson, Tom...
CSREASAM
2007
15 years 8 months ago
Embedded Processor Security
A preliminary model is introduced in this paper whereby data and its associated security properties are treated as a single atomic unit of information in a hardwareonly context. Se...
Brian J. d'Auriol, Tuyen Nguyen, Vo Quoc Hung, Duc...
ISLPED
2010
ACM
234views Hardware» more  ISLPED 2010»
15 years 4 months ago
Diet SODA: a power-efficient processor for digital cameras
Power has become the most critical design constraint for embedded handheld devices. This paper proposes a power-efficient SIMD architecture, referred to as Diet SODA, for DSP appl...
Sangwon Seo, Ronald G. Dreslinski, Mark Woh, Chait...