1563 search results - page 127 / 313 » Flexible instruction processors |
183
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TDSC
2010
15 years 1 months ago
2010
We describe Instruction-Set Randomization (ISR), a general approach for safeguarding systems against any type of code-injection attack. We apply Kerckhoffs' principle to creat...
189
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CODES
2007
IEEE
16 years 26 days ago
2007
IEEE
Caches are notorious for their unpredictability. It is difficult or even impossible to predict if a memory access results in a definite cache hit or miss. This unpredictability i...
174
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MICRO
2007
IEEE
16 years 24 days ago
2007
IEEE
Recently, the microprocessor industry has moved toward chip multiprocessor (CMP) designs as a means of utilizing the increasing transistor counts in the face of physical and micro...
196
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IPCCC
2006
IEEE
16 years 17 days ago
2006
IEEE
Low power has been considered as an important issue in instruction cache (I-cache) designs. Several studies have shown that the I-cache can be tuned to reduce power. These techniq...
197
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ECRTS
2005
IEEE
16 years 4 days ago
2005
IEEE
Cache memories have been extensively used to bridge the gap between high speed processors and relatively slower main memories. However, they are sources of predictability problems...