1563 search results - page 106 / 313 » Flexible instruction processors |
180
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ICS
2005
Tsinghua U.
16 years 3 days ago
2005
Tsinghua U.
We propose an organization for the on-chip memory system of a chip multiprocessor, in which 16 processors share a 16MB pool of 256 L2 cache banks. The L2 cache is organized as a n...
170
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ISCAS
2006
IEEE
16 years 18 days ago
2006
IEEE
Extremely low power consumption is the critical constraint for designing implantable neural decoders that inter- Desired face directly with the nervous system. Typically a system w...
158
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MICRO
2002
IEEE
15 years 11 months ago
2002
IEEE
In a 64-bit processor, many of the data values actually used in computations require much narrower data-widths. In this study, we demonstrate that instruction data-widths exhibit ...
167
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HPCA
2006
IEEE
16 years 7 months ago
2006
IEEE
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...
160
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ICS
2004
Tsinghua U.
15 years 12 months ago
2004
Tsinghua U.
In contemporary out-of-order superscalar design, high IPC is mainly achieved by exposing high instruction level parallelism (ILP). Scaling issue window size can certainly provide ...