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ICCAD
2006
IEEE
124views Hardware» more  ICCAD 2006»
16 years 3 months ago
Robust system level design with analog platforms
An approach to robust system level mixed signal design is presented based on analog platforms. The bottom-up characterization phase of platform components provides accurate perfor...
Fernando De Bernardinis, Pierluigi Nuzzo, Alberto ...
ICCAD
2005
IEEE
107views Hardware» more  ICCAD 2005»
16 years 3 months ago
Projection-based performance modeling for inter/intra-die variations
Large-scale process fluctuations in nano-scale IC technologies suggest applying high-order (e.g., quadratic) response surface models to capture the circuit performance variations....
Xin Li, Jiayong Le, Lawrence T. Pileggi, Andrzej J...
ICCAD
2003
IEEE
115views Hardware» more  ICCAD 2003»
16 years 3 months ago
Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits
This paper presents an efficient method for verifying hazard freedom in timed asynchronous circuits. Timed circuits are a class of asynchronous circuits that utilize explicit tim...
Curtis A. Nelson, Chris J. Myers, Tomohiro Yoneda
FPGA
2010
ACM
250views FPGA» more  FPGA 2010»
16 years 3 months ago
Variation-aware placement for FPGAs with multi-cycle statistical timing analysis
Deep submicron processes have allowed FPGAs to grow in complexity and speed. However, such technology scaling has caused FPGAs to become more susceptible to the effects of process...
Gregory Lucas, Chen Dong, Deming Chen
CVPR
2010
IEEE
16 years 3 months ago
Far-Sighted Active Learning on a Budget for Image and Video Recognition
Active learning methods aim to select the most informative unlabeled instances to label first, and can help to focus image or video annotations on the examples that will most impr...
Sudheendra Vijayanarasimhan, Prateek Jain, Kristen...
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