Sciweavers

2467 search results - page 122 / 494
» Finite State Machines
Sort
View
CODES
2009
IEEE
15 years 10 months ago
Cycle count accurate memory modeling in system level design
In this paper, we propose an effective automatic generation approach for a Cycle-Count Accurate Memory Model (CCAMM) from the Clocked Finite State Machine (CFSM) of the Cycle Accu...
Yi-Len Lo, Mao Lin Li, Ren-Song Tsay
GLVLSI
2007
IEEE
151views VLSI» more  GLVLSI 2007»
15 years 10 months ago
Hand-in-hand verification of high-level synthesis
This paper describes a formal verification methodology of highnthesis (HLS) process. The abstraction level of the input to HLS is so high compared to that of the output that the v...
Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Ma...
EUROPAR
2009
Springer
15 years 10 months ago
A Buffer Space Optimal Solution for Re-establishing the Packet Order in a MPSoC Network Processor
We consider a multi-processor system-on-chip destined for streaming applications. An application is composed of one input and one output queue and in-between, several levels of ide...
Daniela Genius, Alix Munier Kordon, Khouloud Zine ...
ICCTA
2007
IEEE
15 years 10 months ago
Register Sharing Verification During Data-Path Synthesis
The variables of the high-level specifications and the automatically generated temporary variables are mapped on to the data-path registers during data-path synthesis phase of hig...
Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sa...
GECCO
2006
Springer
185views Optimization» more  GECCO 2006»
15 years 10 months ago
Memory analysis and significance test for agent behaviours
Many agent problems in a grid world have a restricted sensory information and motor actions. The environmental conditions need dynamic processing of internal memory. In this paper...
DaeEun Kim