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» FinFETs for nanoscale CMOS digital integrated circuits
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DATE
2005
IEEE
110views Hardware» more  DATE 2005»
15 years 11 months ago
Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters
This paper suggests a practical “hybrid” synthesis methodology which integrates designer-derived analytical models for system-level description with simulation-based models at...
Yu-Tsun Chien, Dong Chen, Jea-Hong Lou, Gin-Kou Ma...
CCECE
2009
IEEE
15 years 10 months ago
A full-rate truly monolithic CMOS CDR for low-cost applications
A truly monolithic clock and data recovery (CDR) circuit for low cost low-end data communication systems has been realized in 0.6ȝm CMOS. The implemented CDR comprises a phase-an...
Bangli Liang, Zhigong Wang, Dianyong Chen, Bo Wang...
DAC
2003
ACM
16 years 7 months ago
A 16-bit mixed-signal microsystem with integrated CMOS-MEMS clock reference
In this work, we report on an unprecedented design where digital, analog, and MEMS technologies are combined to realize a generalpurpose single-chip CMOS microsystem. The converge...
Robert M. Senger, Eric D. Marsman, Michael S. McCo...
ISLPED
2009
ACM
108views Hardware» more  ISLPED 2009»
15 years 10 months ago
Technology flavor selection and adaptive techniques for timing-constrained 45nm subthreshold circuits
We investigate techniques to design 45nm minimum-energy subthreshold CMOS circuits under timing constraints, considering the practical case of an 8-bit multiplier. We first show ...
David Bol, Denis Flandre, Jean-Didier Legat
DAC
2008
ACM
16 years 7 months ago
The mixed signal optimum energy point: voltage and parallelism
An energy optimization is proposed that addresses the nontrivial digital contribution to power and impact on performance in high-speed mixed-signal circuits. Parallel energy and b...
Brian P. Ginsburg, Anantha P. Chandrakasan