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TPHOL
1991
IEEE
15 years 9 months ago
First Steps Towards Automating Hardware Proofs in HOL
D ABSTRACT) Ramayya Kumar, Thomas Kropf, Klaus Schneider University of Karlsruhe,Institute of ComputerDesign and Fault Tolerance (Prof.Dr.D. Schmid) P.O. Box 6980, W-7500 Karlsruhe...
Ramayya Kumar, Thomas Kropf, Klaus Schneider
DAC
2007
ACM
16 years 7 months ago
Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design
Due to shrinking technology, increasing functional frequency and density, and reduced noise margins with supply voltage scaling, the sensitivity of designs to supply voltage noise...
Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram
DAC
2004
ACM
16 years 7 months ago
Defect tolerant probabilistic design paradigm for nanotechnologies
Recent successes in the development and self-assembly of nanoelectronic devices suggest that the ability to manufacture dense nanofabrics is on the near horizon. However, the trem...
Margarida F. Jacome, Chen He, Gustavo de Veciana, ...
ICDCS
2012
IEEE
13 years 8 months ago
Combining Partial Redundancy and Checkpointing for HPC
Today’s largest High Performance Computing (HPC) systems exceed one Petaflops (1015 floating point operations per second) and exascale systems are projected within seven years...
James Elliott, Kishor Kharbas, David Fiala, Frank ...
DSN
2008
IEEE
16 years 22 days ago
Coverage of a microarchitecture-level fault check regimen in a superscalar processor
Conventional processor fault tolerance based on time/space redundancy is robust but prohibitively expensive for commodity processors. This paper explores an unconventional approac...
Vimal K. Reddy, Eric Rotenberg