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» Fault Detection Likelihood of Test Sequence Length
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DSD
2009
IEEE
85views Hardware» more  DSD 2009»
16 years 19 days ago
Thermal-Aware Test Scheduling for Core-Based SoC in an Abort-on-First-Fail Test Environment
—Long test application time and high temperature have become two major issues of system-on-chip (SoC) test. In order to minimize test application times and avoid overheating duri...
Zhiyuan He, Zebo Peng, Petru Eles
DAC
1996
ACM
15 years 10 months ago
Pseudorandom-Pattern Test Resistance in High-Performance DSP Datapaths
The testability of basic DSP datapath structures using pseudorandom built-in self-test techniques is examined. The addition of variance mismatched signals is identified as a testi...
Laurence Goodby, Alex Orailoglu
SEFM
2005
IEEE
15 years 11 months ago
Experimental Evaluation of FSM-Based Testing Methods
The development of test cases is an important issue for testing software, communication protocols and other reactive systems. A number of methods are known for the development of ...
Rita Dorofeeva, Nina Yevtushenko, Khaled El-Fakih,...
GCB
2000
Springer
137views Biometrics» more  GCB 2000»
15 years 9 months ago
Detecting Sporadic Recombination in DNA Alignments with Hidden Markov Models
Conventional phylogenetic tree estimation methods assume that all sites in a DNA multiple alignment have the same evolutionary history. This assumption is violated in data sets fro...
Dirk Husmeier, Frank Wright
ITC
1994
IEEE
151views Hardware» more  ITC 1994»
15 years 10 months ago
Automated Logic Synthesis of Random-Pattern-Testable Circuits
Previous approaches to designing random pattern testable circuits use post-synthesis test point insertion to eliminate random pattern resistant (r.p.r.) faults. The approach taken...
Nur A. Touba, Edward J. McCluskey